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AT91SAM7A2-AI Datasheet(PDF) 59 Page - ATMEL Corporation |
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AT91SAM7A2-AI Datasheet(HTML) 59 Page - ATMEL Corporation |
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59 / 369 page  59 PRELIMINARY AT91SAM7A2 6021A–ATARM–07/04 CM Master Clock Divider Register Name: CM_MDIV Access: Read/Write Base Address: 0x00C • MDIV[6:0]: Master Clock Divider MDIV[6:0] is used to divide the MCK clock and generate the DIVCLK. Default value for MDIV[6:0] is 0x1F. • MDIVKEY[15:0]: Key for Write Access into the CM_MDIV Register Any write in the MDIV[6:0] bits will only be effective if the MDIVKEY[15:0] bits are equal to 0xACDC. These bits are always read at 0. 31 30 29 28 27 26 25 24 MDIVKEY[15:8] 23 22 21 20 19 18 17 16 MDIVKEY[7:0] 15 14 13 12 11 10 9 8 –– ––– –– – 76 543 21 0 –MDIV[6:0] DIVCLK MCK 2MDIV[6:0] 1 ) + ( × --------------------------------------------------- = |
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