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JS28F640P30B85 Datasheet(PDF) 30 Page - Numonyx B.V |
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JS28F640P30B85 Datasheet(HTML) 30 Page - Numonyx B.V |
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30 / 99 page  P30 Datasheet November 2007 30 Order Number: 306666-11 R108 tAPA Page address access - 25 ns 1 R111 tphvh RST# high to ADV# high 30 - ns Clock Specifications R200 fCLK CLK frequency -52 MHz 1,3,5,6 TSOP - 40 MHz R201 tCLK CLK period 19.2 - ns TSOP 25 - ns R202 tCH/CL CLK high/low time 5 - ns R203 tFCLK/RCLK CLK fall/rise time - 3 ns Synchronous Specifications(5,6) R301 tAVCH/L Address setup to CLK 9 - ns 1 R302 tVLCH/L ADV# low setup to CLK 9 - ns R303 tELCH/L CE# low setup to CLK 9 - ns R304 tCHQV / tCLQV CLK to output valid - 17 ns R305 tCHQX Output hold from CLK 3 - ns 1,7 R306 tCHAX Address hold from CLK 10 - ns 1,4,7 R307 tCHTV CLK to WAIT valid - 17 ns 1,7 R311 tCHVL CLK Valid to ADV# Setup 3 - ns 1 R312 tCHTX WAIT Hold from CLK 3 - ns 1,7 Notes: 1. See Figure 11, “AC Input/Output Reference Waveform” on page 28 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package. 6. Synchronous read mode is not supported with TTL level inputs. 7. Applies only to subsequent synchronous reads. Table 17: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3) Num Symbol Parameter Speed Min Max Unit Notes Asynchronous Specifications R1 tAVAV Read cycle time VCC = 1.8 V – 2.0 V 85 - ns VCC = 1.7 V – 2.0 V 88 - 256/512-Mb TSOP packages 95 R2 tAVQV Address to output valid VCC = 1.8 V – 2.0 V -85 ns VCC = 1.7 V – 2.0 V -88 256/512-Mb TSOP packages -95 Table 16: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2) Num Symbol Parameter Min Max Unit Notes |
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