ORLI10G datasheet(39/80 Pages) LATTICE

Part #	ORLI10G

Description	Quad 2.5Gbps, 10Gbps Quad 3.125Gbps, 12.5Gbps Line Interface FPSC

PDF	80 Pages

Scroll/Zoom	100%

Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

Logo

39 / 80 page

Lattice Semiconductor

ORCA ORLI10G Data Sheet

Recommended Board Level Routing For ORLI10G XSBI 10G Interface

The Transmit XSBI port sends clock and data simultaneously as shown in Figure 21.

Figure 21. Clock and Data signals from the TX

The correct clock and data relation required for the XSBI receiver is to have the clock centered in the data eye (as

shown in Figure 22).

Figure 22. Clock and Data Signals at the Receiver

In order to achieve the needed clock and data relationship at the receiver as shown in Figure 21, it is necessary to

swap the P and N clock terminals on the board. This is illustrated in Figure 23. The board level signal swap on the

receiver clock pins effectively inverts the clock phase at the receiving chip creating the correct clock data relation-

ship shown in Figure 22.

CLOCK

DATA

period

1500pS

CLOCK

DATA

ORLI10G Datasheet(PDF) 39 Page - Lattice Semiconductor