ORLI10G datasheet(49/80 Pages) LATTICE

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Lattice Semiconductor

ORCA ORLI10G Data Sheet

Pin Information

Pin Descriptions

This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-

mable I/O. During conﬁguration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.

If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled

after conﬁguration. The pin descriptions in Table 12 and throughout this data sheet show active-low signals with an

overscore. The package pinout tables that follow show this as a signal ending with _N. Therefore, LDC and LDC_N

are equivalent.

Table 12. Pin Descriptions

Symbol

I/O

Description

Dedicated Pins

VDD33

—

3.3 V positive power supply. This power supply is used for 3.3 V conﬁguration RAMs and internal

PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on

the board for proper operation.

VDD15

—

1.5 V positive power supply for internal logic.

VDDIO

—

Positive power supply used by I/O banks.

VSS

—

Ground.

PTEMP

Temperature sensing diode pin. Dedicated input.

RESET

During conﬁguration, RESET forces the restart of conﬁguration and a pull-up is enabled. After con-

ﬁguration, RESET can be used as a general FPGA input or as a direct input, which causes all PLC

latches/Flip-Flops to be asynchronously set/reset.

CCLK

In the master and asynchronous peripheral modes, CCLK is an output which strobes conﬁguration

data in.

In the slave or readback after conﬁguration, CCLK is input synchronous with the data on DIN or

D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in master, peripheral, or

system bus modes.

DONE

As an input, a low level on DONE delays FPGA start-up after conﬁguration.*

As an active-high, open-drain output, a high level on this signal indicates that conﬁguration is com-

plete. DONE has an optional pull-up resistor.

PRGM

is an active-low input that forces the restart of conﬁguration and resets the boundary-scan

circuitry. This pin always has an active pull-up.

RD_CFG

This pin must be held high during device initialization until the INIT pin goes high. This pin always

has an active pull-up.

During conﬁguration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states

all of the I/O.

After conﬁguration, RD_CFG can be selected (via a bit stream option) to activate the TS_ALL func-

tion as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on

RD_CFG

will initiate readback of the conﬁguration data, including PFU output states, starting with

frame address 0.

RD_DATA/TDO

RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides conﬁguration data

out. If used in boundary-scan, TDO is test data out.

CFG_IRQ/MPI_IR

During JTAG, slave, master, and asynchronous peripheral conﬁguration, assertion on this CFG_IRQ

(active-low) indicates an error or errors for block RAM or FPSC initialization.

MPI active-low interrupt

request output, when the MPI is used.

LVDS_R

—

Reference resistor connection for controlled impedance termination of Series 4 FPGA LVDS inputs.

*The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all

other conﬁguration pins (and the activation of all user I/Os) is controlled by a second set of options.

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