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STA308A Datasheet(PDF) 26 Page - STMicroelectronics |
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STA308A Datasheet(HTML) 26 Page - STMicroelectronics |
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26 / 63 page ![]() Registers STA308A 26/63 7.2.4 Configuration register D (0x03) The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. The STA50x recommended use is OM = 10. Setting the MPC bit turns on special processing that corrects the STA50x power device at high power. This mode should lower the THD+N of a full STA50x DDX system at maximum power output and slightly below. This mode will only be operational in OM[1,0] = 01. D7 D6 D5 D4 D3 D2 D1 D0 MPC CSZ4CSZ3CSZ2CSZ1CSZ0 OM1 OM0 11 00 00 10 Bit RW RST Name Description 0RW 0 OM0 DDX power output mode: selects configuration of DDX output. 1RW 1 OM1 OM[1,0] Output stage - mode 00 STA50x/STA51xB - drop compensation 01 Discrete output stage - tapered compensation 10 STA50x/STA51xB - full power mode 11 Variable drop compensation (CSZn bits) Bit RW RST Name Description 2RW 0 CSZ0 Contra size register: when OM[1,0] = 11, this register determines the size of the DDX compensating pulse from 0 clock ticks to 31 clock periods. 3RW 0 CSZ1 4RW 0 CSZ2 5RW 0 CSZ3 6RW 1 CSZ4 CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size …… 11111 31 clock period compensating pulse size Bit RW RST Name Description 7RW 1 MPC Max power correction: setting of 1 enables STA50x correction for THD reduction near maximum power output. |
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