MC145152P2 datasheet(17/24 Pages) FREESCALE

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MC145151-2 and MC145152-2 Electrical Characteristics

MC145151-2 and MC145152-2 Technical Data, Rev. 5

Freescale Semiconductor

Figure 11. Phase Detector/Lock Detector Output Waveforms

Table 6. Frequency Characteristics

(Voltages References to VSS, CL = 50 pF, Input tr = tf =10 ns unless otherwise indicated)

Symbol

Parameter

Test Condition

VDD

- 40

°C

Unit

Min

Max

Min

Max

Min

Max

Input Frequency

(fin, OSCin)

≥ 8, A ≥ 0, N ≥ 8

Vin = 500 mV p-p ac coupled

sine wave

MHz

≥ 8, A ≥ 0, N ≥ 8

Vin = 1 V p-p ac coupled

sine wave

MHz

≥ 8, A ≥ 0, N ≥ 8

Vin = VDD to VSS dc coupled

square wave

MHz

Note: Usually, the PLL's propagation delay from fin to MC plus the setup time of the prescaler determines the upper frequency

limit of the system. The upper frequency limit is found with the following formula: f = P/(tP + tset) where f is the upper frequency

in Hz, P is the lower of the dual modulus prescaler ratios, tP is the fin to MC propagation delay in seconds, and tset is the prescaler

setup time in seconds. For example, with a 5 V supply, the fin to MC delay is 70 ns. If the MC12028A prescaler is used, the setup

time is 16 ns. Thus, if the 64/65 ratio is utilized, the upper frequency limit is f = P/(tP + tset) = 64/(70 + 16) = 744 MHz.

VH=High Voltage Level.

VL=Low Voltage Level.

* At this point, when both fR and fV are in phase, the output is forced to near mid-supply.

NOTE: The PDout generates error pulses during out-of-lock conditions. When locked in phase and frequency the output is high

and the voltage at this pin is determined by the low-pass filter capacitor.

REFERENCE

OSC

÷ R

FEEDBACK

(fin ÷ N)

PDout

HIGH IMPEDANCE

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