MSC8122 datasheet(30/48 Pages) FREESCALE

30 / 48 page

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Electrical Characteristics

Freescale Semiconductor

Figure 15 shows DSI asynchronous write signals timing.

Figure 16 shows DSI asynchronous broadcast write signals timing.

Figure 15. Asynchronous Single- and Dual-Strobe Modes Write Timing Diagram

Figure 16. Asynchronous Broadcast Write Timing Diagram

HD[0–63]

100

101

102

201

202

109

106

HWBSn2

108

110

111

112

HDBSn1

HTA4

HTA3

Notes:

Used for single-strobe mode access.

Used for dual-strobe mode access.

HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation.

HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.

HA[11–29]

HCS

HCID[0–4]

HDST

HRW1

HRDS2

HD[0–63]

100

101

102

201

202

HWBSn2

112

HDBSn1

Notes:

Used for single-strobe mode access.

Used for dual-strobe mode access.

HA[11–29]

HCS

HCID[0–4]

HDST

HRW1

HRDS2

MSC8122 Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc

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