MSC8122 datasheet(38/48 Pages) FREESCALE

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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

704

Boundary scan input data set-up time

5.0

—

705

Boundary scan input data hold time

20.0

—

706

TCK low to output data valid

0.0

30.0

707

TCK low to output high impedance

0.0

30.0

708

TMS, TDI data set-up time

5.0

—

709

TMS, TDI data hold time

20.0

—

710

TCK low to TDO data valid

0.0

20.0

711

TCK low to TDO high impedance

0.0

20.0

712

TRST assert time

100.0

—

713

TRST set-up time to TCK low

30.0

—

Note:

All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

Figure 29. Test Clock Input Timing Diagram

Figure 30. Boundary Scan (JTAG) Timing Diagram

Table 30. JTAG Timing (continued)

No.

Characteristics

All

frequencies

Unit

Min

Max

TCK

(Input)

VIH

VIL

701

702

703

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

VIH

VIL

Input Data Valid

Output Data Valid

705

704

706

707

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