MSC8122 datasheet(36/48 Pages) FREESCALE

36 / 48 page

MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Freescale Semiconductor

2.5.10.4

SMII Mode

2.5.11

GPIO Timing

Table 27. SMII Mode Signal Timing

No.

Characteristics

Min

Max

Unit

808

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time

1.0

—

809

ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time

1.0

—

810

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay

•

1.1 V core.

•

1.2 V core.

1.51

6.02

5.02

Notes:

Measured using a 5 pF load.

Measured using a 15 pF load.

Figure 26. SMII Mode Signal Timing

Table 28. GPIO Timing

No.

Characteristics

Ref = CLKIN

Ref = CLKOUT

(1.2 V only)

Unit

Min

Max

Min

Max

601

REFCLK edge to GPIO out valid (GPIO out delay time)

—

6.1

—

6.9

602

REFCLK edge to GPIO out not valid (GPIO out hold time)

1.1

—

1.3

—

603

REFCLK edge to high impedance on GPIO out

—

5.4

—

6.2

604

GPIO in valid to REFCLK edge (GPIO in set-up time)

3.5

—

3.7

—

605

REFCLK edge to GPIO in not valid (GPIO in hold time)

0.5

—

0.5

—

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD

Valid

810

809

808

MSC8122 Datasheet(PDF) 36 Page - Freescale Semiconductor, Inc

MSC8122 Datasheet(HTML) 36 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL