MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15

Hardware Design Considerations

Freescale Semiconductor

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3.2

Power Supply Design Considerations

When used as a drop-in replacement in MSC8102 applications or when implementing a new design, use the guidelines

described in Migrating Designs from the MSC8102 to the MSC8122 (AN2716) and the MSC8122 Design Checklist (AN3374

for optimal system performance. MSC8122 and MSC8126 Power Circuit Design Recommendations and Examples (AN2937)

provides detailed design information. See Section 2.5.2 for start-up timing specifications.

Figure 33 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the

decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on

the package pins should not drop below the minimum specified voltage level even for a very short spikes. This can be achieved

by using the following guidelines:

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For the core supply, use a voltage regulator rated at 1.2 V with nominal rating of at least 3 A. This rating does not

reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has

better voltage recovery time than supplies with lower current ratings.

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Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three

capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount

at least one of the capacitors directly below the MSC8122 device.

GND

pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the

GND

planes.

All output pins on the MSC8122 have fast rise and fall times. PCB trace interconnection length should be minimized to

minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to

the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in

synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.

Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to

proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create

Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:

Figure 33. Core Power Supply Decoupling

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Power supply

or

Voltage Regulator

High frequency capacitors

(very low ESR and ESL)

Bulk/Tantalum capacitors

with low ESR and ESL

MSC8122

Maximum IR drop

of 15 mV at 1 A

Note: Use at least three capacitors.

One 0.01 µF capacitor

for every 3 core supply

pads.

1.2 V

Each capacitor must be at least 150

μF.