R8C2K datasheet(320/471 Pages) RENESAS

320 / 471 page

R8C/2K Group, R8C/2L Group

16. Timers

Rev.1.10

Dec 21, 2007

Page 303 of 450

REJ09B0406-0110

Figure 16.141 Registers TRDSR0 to TRDSR1 in PWM3 Mode

Timer RD Status Register i (i = 0 or 1)

Symbol

Address

After Reset

TRDSR0

0143h

11100000b

TRDSR1

0153h

11000000b

Bit Symbol

Bit Name

Function

NOTES:

2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).

—

(b7-b6)

—

Nothing is assigned. If necessary, set to 0.

When read, the content is 1.

The w riting results are as follow s:

• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.

• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains

1 even if it is set to 1 from 0 after reading, and w riting 0).

• This bit remains unchanged if 1 is w ritten to it.

Input capture/compare match flag D

[Source for setting this bit to 0]

Write 0 after read(1).

[Source for setting this bit to 1]

When the value in the TRDi register

matches w ith the value in the TRDGRDi

OVF

Input capture/compare match flag C

[Source for setting this bit to 0]

Write 0 after read(1).

[Source for setting this bit to 1]

When the value in the TRDi register

matches w ith the value in the TRDGRCi

IMFC

Overflow flag

[Source for setting this bit to 0]

Write 0 after read(1).

[Source for setting this bit to 1]

When the TRDi register overflow s.

IMFB

Input capture/compare match flag A

[Source for setting this bit to 0]

Write 0 after read(1).

[Source for setting this bit to 1]

When the value in the TRDi register

matches w ith the value in the TRDGRAi

Input capture/compare match flag B

[Source for setting this bit to 0]

Write 0 after read(1).

[Source for setting this bit to 1]

When the value in the TRDi register

matches w ith the value in the TRDGRBi

IMFA

b7 b6 b5 b4 b3 b2

IMFD

b1 b0

UDF

Underflow flag(1)

This bit is disabled in PWM3 mode.

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