SH7261 datasheet(67/1348 Pages) RENESAS

67 / 1348 page

Section 2 CPU

Rev. 2.00 Sep. 07, 2007 Page 35 of 1312

REJ09B0320-0200

Addressing Mode

Instruction Format

Effective Address Calculation

Equation

with displacement

@(disp:4,Rn)

The effective address is the sum of Rn and

a 4-bit displacement (disp). The value of disp is

zero-extended, and remains unchanged for

a byte operation, is doubled for a word

operation, and is quadrupled for a longword

operation.

Rn + disp

× 1/2/4

1/2/4

disp

(zero-extended)

Byte:

Rn + disp

Word:

Rn + disp

× 2

Longword:

Rn + disp

× 4

with displacement

@(disp:12,Rn)

The effective address is the sum of Rn and

a 12-bit displacement (disp).

The value of disp is zero-extended.

disp

(zero-extended)

Rn + disp

Byte:

Rn + disp

Word:

Rn + disp

Longword:

Rn + disp

Indexed register

indirect

@(R0,Rn)

The effective address is the sum of Rn and R0.

Rn + R0

GBR indirect with

displacement

@(disp:8,GBR)

The effective address is the sum of GBR value

and an 8-bit displacement (disp). The value of

disp is zero-extended, and remains unchanged

for a byte operation, is doubled for a word

operation, and is quadrupled for a longword

operation.

GBR

1/2/4

GBR

+ disp

× 1/2/4

disp

(zero-extended)

Byte:

GBR + disp

Word:

GBR + disp

× 2

Longword: GBR

+ disp

× 4

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