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SH7261 Datasheet(PDF) 68 Page - Renesas Technology Corp

Part # SH7261
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
PDF  1348 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7261 Datasheet(HTML) 68 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 2.00 Sep. 07, 2007 Page 36 of 1312
REJ09B0320-0200
Addressing Mode
Instruction Format
Effective Address Calculation
Equation
Indexed GBR
indirect
@(R0,GBR)
The effective address is the sum of GBR value
and R0.
GBR
R0
GBR + R0
+
GBR + R0
TBR duplicate
indirect with
displacement
@@ (disp:8,TBR)
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
TBR
TBR
+ disp
× 4
(TBR
+ disp
× 4)
4
+
disp
(zero-extended)
×
Contents of
address (TBR +
disp
× 4)
PC indirect with
displacement
@(disp:8,PC)
The effective address is the sum of PC value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
PC
H'FFFFFFFC
PC + disp
× 2
or
PC & H'FFFFFFFC
+ disp
× 4
+
2/4
×
&
(for longword)
disp
(zero-extended)
Word:
PC + disp
× 2
Longword:
PC &
H'FFFFFFFC +
disp
× 4
PC relative
disp:8
The effective address is the sum of PC value
and the value that is obtained by doubling the
sign-extended 8-bit displacement (disp).
PC
2
+
×
disp
(sign-extended)
PC + disp
× 2
PC + disp
× 2



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