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HD6417606 Datasheet(PDF) 58 Page - Renesas Technology Corp |
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HD6417606 Datasheet(HTML) 58 Page - Renesas Technology Corp |
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58 / 532 page  Section 2 CPU Rev. 4.00 Sep. 13, 2007 Page 32 of 502 REJ09B0239-0400 Table 2.9 Instruction Formats Instruction Format Source Operand Destination Operand Sample Instruction 0 type xxxx xxxx xxxx xxxx 15 0 NOP nnnn : register direct MOVT Rn Control register or system register nnnn : register direct STS MACH,Rn n type xxxx nnnn xxxx xxxx 15 0 Control register or system register nnnn : pre- decrement register indirect STC.L SR,@-Rn mmmm : register direct Control register or system register LDC Rm,SR mmmm : post- increment register indirect Control register or system register LDC.L @Rm+,SR mmmm : register indirect JMP @Rm m type xxxx mmmm xxxx xxxx 15 0 PC relative using Rm BRAF Rm |
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