HD6417606 datasheet(29/532 Pages) RENESAS

29 / 532 page

Section 1 Overview

Rev. 4.00 Sep. 13, 2007 Page 3 of 502

REJ09B0239-0400

Interrupt controller (INTC):

• Supports nine external interrupt pins (NMI, IRQ7 to IRQ0)

• On-chip peripheral interrupt: Priority level is independently selected for each module

• Vector address: Specified vector address for each interrupt source

User debugging interface (H-UDI):

• Supports the JTAG interface emulator

• JTAG standard pins arranged

Clock pulse generator (CPG):

• Clock mode: Clock source selectable between an external supply and crystal resonator

• Three types of clocks generated:

 CPU clock: 100 MHz (max.)

 Bus clock: 50 MHz (max.)

 Peripheral clock: 50 MHz (max.)

• Supports power-down modes:

 Sleep mode

 Software standby mode

• Selection of four types of clock modes (PLL2 ×2/×4 and clock/crystal resonator are selectable)

Host interface (HIF):

• 1 kbyte × 2 banks: in total 2-kbyte buffer RAM

• The buffer RAM and the external device are connected in parallel via 16 data pins

• The buffer RAM and the CPU of this LSI are connected in parallel via internal bus

• The external device can access the desired register after the register index has been specified.

(However, when the buffer RAM is accessed successively, the address is updated

automatically.)

• Selection of endian mode

• Interrupt requested to the external device

• Internal interrupt requested to the CPU of this LSI

• Booting from the buffer RAM is enabled if the external device has stored the instruction code

in the buffer RAM

HD6417606 Datasheet(PDF) 29 Page - Renesas Technology Corp