HD6417606 datasheet(13/532 Pages) RENESAS

13 / 532 page

Rev. 4.00 Sep. 13, 2007 Page xiii of xxvi

12.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 241

12.3.5 Serial Mode Register (SCSMR)............................................................................ 241

12.3.6 Serial Control Register (SCSCR).......................................................................... 245

12.3.7 Serial Status Register (SCFSR) ............................................................................ 249

12.3.8 Bit Rate Register (SCBRR) .................................................................................. 257

12.3.9 FIFO Control Register (SCFCR) .......................................................................... 263

12.3.10 FIFO Data Count Register (SCFDR) .................................................................... 267

12.3.11 Serial Port Register (SCSPTR) ............................................................................. 268

12.3.12 Line Status Register (SCLSR) .............................................................................. 272

12.4

Operation ........................................................................................................................... 273

12.4.1 Overview............................................................................................................... 273

12.4.2 Operation in Asynchronous Mode ........................................................................ 275

12.4.3 Synchronous Mode ............................................................................................... 286

12.5

SCIF Interrupts .................................................................................................................. 294

12.6

Serial Port Register (SCSPTR) and SCIF Pins .................................................................. 295

12.7

Usage Notes ....................................................................................................................... 298

Section 13 Host Interface (HIF).........................................................................301

13.1

Features.............................................................................................................................. 301

13.2

Input/Output Pins ...............................................................................................................303

13.3

Parallel Access ................................................................................................................... 304

13.3.1 Operation .............................................................................................................. 304

13.3.2 Connection Method............................................................................................... 304

13.4

Register Descriptions ......................................................................................................... 305

13.4.1 HIF Index Register (HIFIDX) .............................................................................. 305

13.4.2 HIF General Status Register (HIFGSR)................................................................ 307

13.4.3 HIF Status/Control Register (HIFSCR) ................................................................ 307

13.4.4 HIF Memory Control Register (HIFMCR) ........................................................... 310

13.4.5 HIF Internal Interrupt Control Register (HIFIICR) .............................................. 312

13.4.6 HIF External Interrupt Control Register (HIFEICR) ............................................ 313

13.4.7 HIF Address Register (HIFADR) ......................................................................... 314

13.4.8 HIF Data Register (HIFDATA) ............................................................................ 315

13.4.9 HIF Boot Control Register (HIFBCR).................................................................. 315

13.4.10 HIFDREQ Trigger Register (HIFDTR) ................................................................ 316

13.4.11 HIF Bank Interrupt Control Register (HIFBICR) ................................................. 317

13.5

Memory Map ..................................................................................................................... 319

13.6

Interface (Basic)................................................................................................................. 320

13.7

Interface (Details) .............................................................................................................. 321

13.7.1 HIFIDX Write/HIFGSR Read .............................................................................. 321

13.7.2 Reading/Writing of HIF Registers other than HIFIDX and HIFGSR................... 321

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