HD6432351 datasheet(850/1025 Pages) RENESAS

850 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 816 of 988

REJ09B0330-0300

MRB—DTC Mode Register B

H'F800–H'FBFF

DTC

CHNE

Undefined

—

DISEL

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Undefined

—

Bit

Initial value

Read/Write

DTC Chain Transfer Enable

End of DTC data transfer

DTC chain transfer

DTC Interrupt Select

Reserved

Only 0 should be written to these bits

After a data transfer ends, the CPU interrupt is

disabled unless the transfer counter is 0

After a data transfer ends, the CPU interrupt is enabled

SAR—DTC Source Address Register

H'F800–H'FBFF

DTC

Bit

Initial value

Read/Write

43210

- - -

Specifies transfer data source address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

Unde-

fined

——

—

DAR—DTC Destination Address Register

H'F800–H'FBFF

DTC

Bit

Initial value

Read/Write

43210

- - -

Specifies transfer data destination address

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

HD6432351 Datasheet(PDF) 850 Page - Renesas Technology Corp

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