HD6432351 datasheet(852/1025 Pages) RENESAS

852 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 818 of 988

REJ09B0330-0300

TCR3—Timer Control Register 3

H'FE80

TPU3

CCLR2

R/W

CCLR1

R/W

CCLR0

R/W

CKEG1

R/W

CKEG0

R/W

TPSC0

R/W

TPSC2

R/W

TPSC1

R/W

Bit

Initial value

Read/Write

TCNT clearing disabled

TCNT cleared by TGRA compare match/input capture

TCNT cleared by TGRB compare match/input capture

TCNT clearing disabled

TCNT cleared by TGRC compare match/input capture*

TCNT cleared by TGRD compare match/input capture*

Counter Clear

Clock Edge

—

Count at rising edge

Count at falling edge

Count at both edges

Internal clock: counts on

φ/1

Internal clock: counts on

φ/4

Internal clock: counts on

φ/16

Internal clock: counts on

φ/64

External clock: counts on TCLKA pin input

Internal clock: counts on

φ/1024

Internal clock: counts on

φ/256

Internal clock: counts on

φ/4096

Timer Prescaler

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

TCNT cleared by counter clearing for another channel

performing synchronous clearing/synchronous operation*

Notes: 1.

Synchronous operation setting is performed by setting the SYNC

bit in TSYR to 1.

When TGRC or TGRD is used as a buffer register, TCNT is not

cleared because the buffer register setting has priority, and

compare match/input capture does not occur.

HD6432351 Datasheet(PDF) 852 Page - Renesas Technology Corp

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