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HD6432351 Datasheet(PDF) 854 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 854 Page - Renesas Technology Corp |
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854 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 820 of 988 REJ09B0330-0300 TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 0 1 TGR3B I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 TGR3A is output compare register TGR3A I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: *: Don’t care 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 0 IOA0 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W Bit Initial value Read/Write : : : TGR3A is input capture register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA3 pin Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down TGR3B is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3B is input capture register Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCB3 pin Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down*1 Note: 1. If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and φ/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur. Legend: *: Don’t care |
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