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HD6432351 Datasheet(PDF) 853 Page - Renesas Technology Corp |
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HD6432351 Datasheet(HTML) 853 Page - Renesas Technology Corp |
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853 / 1025 page  Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 819 of 988 REJ09B0330-0300 TMDR3—Timer Mode Register 3 H'FE81 TPU3 7 — 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 0 MD0 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W Bit Initial value Read/Write : : : 0 Buffer Operation B TGRB operates normally 0 Buffer Operation A TGRA operates normally 0 1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — Mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * Notes: 1. 2. Legend: *: Don’t care MD3 is a reserved bit. In a write, it should always be written with 0. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA and TGRC used together for buffer operation 1 TGRB and TGRD used together for buffer operation 1 |
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