HD6432142 datasheet(343/1177 Pages) RENESAS

343 / 1177 page

Section 10 14-Bit PWM Timer (PWMX)

Rev. 4.00 Sep 27, 2006 page 299 of 1130

REJ09B0327-0400

10.3

Bus Master Interface

DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the

on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these

registers, it therefore uses an 8-bit temporary register (TEMP).

These registers are written and read as follows (taking the example of the CPU interface).

• Write

When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the

lower byte is written, the lower-byte write data and TEMP value are combined, and the

combined 16-bit value is written in the register.

• Read

When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte

value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in

TEMP is transferred to the CPU.

These registers should always be accessed 16 bits at a time using an MOV instruction (by word

access or two consecutive byte accesses), and the upper byte should always be accessed before the

lower byte. Correct data will not be transferred if only the upper byte or only the lower byte is

accessed. Also note that a bit-manipulation instruction cannot be used to access these registers.

Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly.

Example 1: Write to DACNT

MOV.W R0, @DACNT

;

Write R0 contents to DACNT

Example 2: Read DADRA

MOV.W @DADRA, R0

;

Transfer contents of DADRA to R0

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