HD6432142 datasheet(546/1177 Pages) RENESAS

Part #	HD6432142

Description	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1177 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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546 / 1177 page

Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 502 of 1130

REJ09B0327-0400

Bit 7

MLS

Description

MSB-first

(Initial value)

LSB-first

Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data

and the acknowledge bit, in master mode with the I

2C bus format. When WAIT is set to 1, after the

fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins

(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the

acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred

consecutively with no wait inserted.

The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the

WAIT setting.

The setting of this bit is invalid in slave mode.

Bit 6

WAIT

Description

Data and acknowledge bits transferred consecutively

(Initial value)

Wait inserted between data and acknowledge bits

HD6432142 Datasheet(PDF) 546 Page - Renesas Technology Corp