HD6432142 datasheet(548/1177 Pages) RENESAS

548 / 1177 page

Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 504 of 1130

REJ09B0327-0400

Bit 2

Bit 1

Bit 0

Bits/Frame

BC2

BC1

BC0

Synchronous Serial Format

2C Bus Format

(Initial value)

16.2.5

2C Bus Control Register (ICCR)

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

ICE

R/W

IEIC

R/W

MST

R/W

TRS

R/W

ACKE

R/W

SCP

BBSY

R/W

IRIC

R/(W)*

ICCR is an 8-bit readable/writable register that enables or disables the I

2C bus interface, enables or

disables interrupts, selects master or slave mode and transmission or reception, enables or disables

acknowledgement, confirms the I

2C bus interface bus status, issues start/stop conditions, and

performs interrupt flag confirmation.

ICCR is initialized to H'01 by a reset and in hardware standby mode.

Bit 7—I

2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be

used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer

operations are enabled. When ICE is cleared to 0, the I

2C bus interface module is halted and its

internal states are cleared.

The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can

be accessed when ICE is 1.

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