HD6432142 datasheet(551/1177 Pages) RENESAS

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Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 507 of 1130

REJ09B0327-0400

Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the

acknowledge bit returned from the receiving device when using the I

2C bus format is to be ignored

and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,

performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received

acknowledge bit is not indicated by the ACKB bit, which is always 0.

In the H8S/2148 Group and H8S/2147N, the DTC can be used to perform continuous transfer. The

DTC is activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the

other being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on

completion of data transmission, regardless of the value of the acknowledge bit. When the ACKE

bit is 1, the TDRE, IRIC, and IRTR flags are set on completion of data transmission when the

acknowledge bit is 0, and the IRIC flag alone is set on completion of data transmission when the

acknowledge bit is 1.

When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified

number of data transfers have been executed. Consequently, interrupts are not generated during

continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the

ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled.

Depending on the receiving device, the acknowledge bit may be significant, in indicating

completion of processing of the received data, for instance, or may be fixed at 1 and have no

significance.

Bit 3

ACKE

Description

The value of the acknowledge bit is ignored, and continuous transfer

is performed

(Initial value)

If the acknowledge bit is 1, continuous transfer is interrupted

Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I

2C bus (SCL, SDA)

is busy or free. In master mode, this bit is also used to issue start and stop conditions.

A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting

BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,

clearing BBSY to 0.

To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit

start condition is issued in the same way. To issue a stop condition, use a MOV instruction to

write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I

2C bus

interface must be set to master transmit mode before issuing a start condition. MST and TRS

should both be set to 1 before writing 1 in BBSY and 0 in SCP.

HD6432142 Datasheet(PDF) 551 Page - Renesas Technology Corp

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