HD6432142 datasheet(554/1177 Pages) RENESAS

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Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 510 of 1130

REJ09B0327-0400

When, with the I

2C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags

must be checked in order to identify the source that set IRIC to 1. Although each source has a

corresponding flag, caution is needed at the end of a transfer.

When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The

IRTR flag (the DTC start request flag) is not set at the end of a data transfer up to detection of a

retransmission start condition or stop condition after a slave address (SVA) or general call address

match in I

2C bus format slave mode.

Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.

The IRIC and IRTR flags are not cleared at the end of the specified number of transfers in

continuous transfer using the DTC. The TDRE or RDRF flag is cleared, however, since the

specified number of ICDR reads or writes have been completed.

Table 16.3 shows the relationship between the flags and the transfer states.

Table 16.3

Flags and Transfer States

MST

TRS

BBSY ESTP STOP IRTR

AASX

AAS

ADZ

ACKB State

1/0

Idle state (flag clearing

required)

Start condition issuance

Start condition established

1/0

0/1

Master mode wait

1/0

0/1

Master mode transmit/

receive end

1/0

Arbitration lost

SAR match by first frame in

slave mode

General call address match

SARX match

1/0

0/1

Slave mode

transmit/receive end

(except after SARX match)

1/0

Slave mode

transmit/receive end (after

SARX match)

1/0

0/1

Stop condition detected

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