HD6432142 datasheet(587/1177 Pages) RENESAS

587 / 1177 page

Section 16 I

2C Bus Interface [Option]

Rev. 4.00 Sep 27, 2006 page 543 of 1130

REJ09B0327-0400

Table 16.6

2C Bus Timing (SCL and SDA Output)

Item

Symbol

Output Timing

Unit

Notes

SCL output cycle time

SCLO

28t

cyc to 256tcyc

SCL output high pulse width

SCLHO

0.5t

SCLO

Figure 26.28

(reference)

SCL output low pulse width

SCLLO

0.5t

SCLO

SDA output bus free time

BUFO

0.5t

SCLO –1tcyc

Start condition output hold time

STAHO

0.5t

SCLO –1tcyc

Retransmission start condition output

setup time

STASO

SCLO

Stop condition output setup time

STOSO

0.5t

SCLO +2tcyc

Data output setup time (master)

SDASO

SCLLO –3tcyc

Data output setup time (slave)

SCLL –(6tcyc or 12tcyc

Data output hold time

SDAHO

cyc

Note:

cyc when IICX is 0, 12tcyc when 1.

• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing

therefore depends on the system clock cycle t

cyc, as shown in I

2C Bus Timing in section 26,

Electrical Characteristics, and as shown in table 26.10. Note that the I

2C bus interface AC

timing specifications will not be met with a system clock frequency of less than 5 MHz.

• The I2C bus interface specification for the SCL rise time t

sr is under 1000 ns (300 ns for high-

speed mode). In master mode, the I

2C bus interface monitors the SCL line and synchronizes

one bit at a time during communication. If t

sr (the time for SCL to go from low to VIH) exceeds

the time determined by the input clock of the I

2C bus interface, the high period of SCL is

extended. The SCL rise time is determined by the pull-up resistance and load capacitance of

the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance

and load capacitance so that the SCL rise time does not exceed the values given in the table

below.

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