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HD6432142 Datasheet(PDF) 591 Page - Renesas Technology Corp

Part # HD6432142
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1177 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432142 Datasheet(HTML) 591 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 547 of 1130
REJ09B0327-0400
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
SDA
SCL
Internal clock
BBSY bit
Master receive mode
ICDR reading
prohibited
Bit 0
A
8
9
Stop condition
(a)
Start condition
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
• Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition issuance is done and determined the start condition, write the transmit data to ICDR,
as shown below.



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