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HD6432142 Datasheet(PDF) 593 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 593 Page - Renesas Technology Corp |
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593 / 1177 page ![]() Section 16 I 2C Bus Interface [Option] Rev. 4.00 Sep 27, 2006 page 549 of 1130 REJ09B0327-0400 • Notes on I2C Bus Interface Stop Condition Instruction Issuance If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising of the 9th SCL clock, issue the stop condition instruction after reading SCL and determining it to be low, as shown below. Stop condition SCL IRIC [1] Determination of SCL = low 9th clock VIH High period secured [2] Stop condition instruction issuance SDA As waveform rise is late, SCL is detected as low Figure 16.20 Timing of Stop Condition Issuance |
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