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HD6432142 Datasheet(PDF) 610 Page - Renesas Technology Corp |
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HD6432142 Datasheet(HTML) 610 Page - Renesas Technology Corp |
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610 / 1177 page ![]() Section 17 Keyboard Buffer Controller Rev. 4.00 Sep 27, 2006 page 566 of 1130 REJ09B0327-0400 Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output. Bit 6 KCLKO Description 0 Keyboard buffer controller clock I/O pin is low 1 Keyboard buffer controller clock I/O pin is high (Initial value) Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output. Bit 5 KDO Description 0 Keyboard buffer controller data I/O pin is low 1 Keyboard buffer controller data I/O pin is high (Initial value) Bit 4—Reserved: This bit cannot be modified and is always read as 1. Bits 3 to 0—Receive Counter (RXCR3 to RXCR0): These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received. Bit 3 Bit 2 Bit 1 Bit 0 RXCR3 RXCR2 RXCR1 RXCR0 Receive Data Contents 0 0 0 0 — (Initial value) 1 Start bit 1 0 KB0 1 KB1 1 0 0 KB2 1 KB3 1 0 KB4 1 KB5 10 00KB6 1 KB7 1 0 Parity bit 1— 1 ——— |
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