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HD6432142 Datasheet(PDF) 618 Page - Renesas Technology Corp

Part # HD6432142
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1177 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432142 Datasheet(HTML) 618 Page - Renesas Technology Corp

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Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 574 of 1130
REJ09B0327-0400
Read KBCRL
KBF = 0?
RXCR3 to RXCR0
≥
B'1001?
Disable receive abort
requests
Yes
Start
Receive state
Read KBCRH
Processing 1
KCLKO = 0
(receive abort request)
Retransmit
command transmission
(data)?
KBE = 0
(disable KBBR reception
and clear receive counter)
Set start bit
(KDO = 0)
Clear I/O inhibit
(KCLKO = 1)
Transmit data
To transmit operation
KBE = 0
(disable KBBR reception
and clear receive counter)
KBE = 1
(enable KB operation)
Clear I/O inhibit
(KCLKO = 1)
To receive operation
[1] Read KBCRL, and if KBF = 1,
perform processing 1.
[2] Read KBCRH, and if the value of
bits RXCR3 to RXCR0 is less than
B'1001, write 0 in KCLKO to abort
reception.
If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, wait
until stop bit reception is
completed, then perform receive
data processing, and proceed to
the next operation.
[3] If the value of bits RXCR3 to
RXCR0 is B'1001 or greater, the
parity bit is being received. With
the PS2 interface, a receive abort
request following parity bit
reception is disabled. Wait until
stop bit reception is completed,
perform receive data processing
and clear the KBF flag, then
proceed to the next operation.
Yes
No
No
No
Yes
[1]
[2]
[3]
Figure 17.7 Sample Receive Abort Processing Flowchart



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