HD6432142 datasheet(310/1177 Pages) RENESAS

310 / 1177 page

Section 8 I/O Ports

Rev. 4.00 Sep 27, 2006 page 266 of 1130

REJ09B0327-0400

8.11.2

Table 8.22 summarizes the port A registers.

Table 8.22

Port A Registers

Name

Abbreviation

R/W

Initial Value

Address*

Port A data direction register

PADDR

H'00

H'FFAB*

Port A output data register

PAODR

R/W

H'00

H'FFAA

Port A input data register

PAPIN

Undefined

H'FFAB*

Notes: 1. Lower 16 bits of the address.

2. PADDR and PAPIN have the same address.

Port A Data Direction Register (PADDR)

Bit

765

432

PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR

Initial value

000

Read/Write

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A.

Setting a PADDR bit to 1 makes the corresponding port A pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

PADDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in

software standby mode.

Port A Output Data Register (PAODR)

Bit

765

432

PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR

Initial value

000

Read/Write

R/W

PAODR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to

PA0). PAODR can always be read or written to, regardless of the contents of PADDR.

HD6432142 Datasheet(PDF) 310 Page - Renesas Technology Corp

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