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SH7052 Datasheet(PDF) 130 Page - Renesas Technology Corp

Part # SH7052
Description  SuperHTM RISC engine
PDF  919 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7052 Datasheet(HTML) 130 Page - Renesas Technology Corp

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104
7.2.3
User Break Bus Cycle Register (UBBR)
Bit:
15
14
13
12
11
10
9
8
——
——
———
—
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
CP1
CP0
ID1
ID0
RW1
RW0
SZ1
SZ0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that selects from
among the following four break conditions:
1. CPU cycle/DMA cycle
2. Instruction fetch/data access
3. Read/write
4. Operand size (byte, word, longword)
UBBR is initialized to H'0000 by a power on reset and in module standby mode. It is not
initialized in software standby mode.
• Bits 15 to 8—Reserved: These bits always read 0. The write value should always be 0.
• Bits 7 and 6—CPU Cycle/DMA Cycle Select (CP1, CP0): These bits designate break
conditions for CPU cycles or DMA cycles.
Bit 7: CP1
Bit 6: CP0
Description
0
0
No user break interrupt occurs
(Initial value)
1
Break on CPU cycles
1
0
Break on DMA cycles
1
Break on both CPU and DMA cycles



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