SH7052 datasheet(132/919 Pages) RENESAS

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7.2.4

User Break Control Register (UBCR)

Bit:

——

———

—

Initial value:

R/W:

Bit:

—

CKS1

CKS0

UBID

Initial value:

R/W:

R/W

The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or

disables user break interrupts and (2) sets the pulse width of the

UBCTRG signal output in the

event of a break condition match.

UBCR is initialized to H'0000 by a power-on reset and in module standby mode. It is not

initialized in software standby mode.

• Bits 15 to 3—Reserved: These bits always read 0. The write value should always be 0.

• Bits 2 and 1—Clock Select 1 and 0 (CKS1, CKS0): These bits specify the pulse width of the

UBCTRG signal output in the event of a condition match.

Bit 2: CKS1

Bit 1: CKS0

Description

UBCTRG pulse width is

(Initial value)

UBCTRG pulse width is

φ/4

UBCTRG pulse width is

φ/8

UBCTRG pulse width is

φ/16

Note:

φ: Internal clock

• Bit 0—User Break Disable (UBID): Enables or disables user break interrupt request generation

in the event of a user break condition match.

Bit 0: UBID

Description

User break interrupt request is enabled

(Initial value)

User break interrupt request is disabled

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