SH7052 datasheet(128/919 Pages) RENESAS

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UBARL:

Bit:

UBA15

UBA14

UBA13

UBA12

UBA11

UBA10

UBA9

UBA8

Initial value:

R/W:

R/W

Bit:

UBA7

UBA6

UBA5

UBA4

UBA3

UBA2

UBA1

UBA0

Initial value:

R/W:

R/W

The user break address register (UBAR) consists of user break address register H (UBARH) and

user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH

stores the upper bits (bits 31 to 16) of the address of the break condition, while UBARL stores the

lower bits (bits 15 to 0). UBARH and UBARL are initialized to H'0000 by a power-on reset and in

module standby mode. They are not initialized in software standby mode.

• UBARH Bits 15 to 0—User Break Address 31 to 16 (UBA31 to UBA16): These bits store the

upper bit values (bits 31 to 16) of the address of the break condition.

• UBARL Bits 15 to 0—User Break Address 15 to 0 (UBA15 to UBA0): These bits store the

lower bit values (bits 15 to 0) of the address of the break condition.

7.2.2

User Break Address Mask Register (UBAMR)

UBAMRH:

Bit:

UBM31

UBM30

UBM29

UBM28

UBM27

UBM26

UBM25

UBM24

Initial value:

R/W:

R/W

Bit:

UBM23

UBM22

UBM21

UBM20

UBM19

UBM18

UBM17

UBM16

Initial value:

R/W:

R/W

SH7052 Datasheet(PDF) 128 Page - Renesas Technology Corp

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