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SH7052 Datasheet(PDF) 161 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 161 Page - Renesas Technology Corp |
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161 / 919 page ![]() 135 IW31 and IW30 specify the number of idle cycles required after a CS3 space read either to read other external spaces, or for this chip, to perform write accesses. In the same manner, IW21 and IW20 specify the number of idle cycles after a CS2 space read, IW11 and IW10, the number after a CS1 space read, and IW01 and IW00, the number after a CS0 space read. 0 to 3 idle cycles can be specified. 8.4.2 Simplification of Bus Cycle Start Detection For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles designated by the CW3 to CW0 bits of BCR2 occur. However, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits. When idle cycles already exist between access cycles, waits are not inserted. Figure 8.8 shows an example. A continuous access idle is specified for CSn space, and CSn space is consecutively write-accessed. CK CSn RD WRH, WRL Data CSn space access CSn space access Idle cycle Address T1 T2 T1 T2 Tidle Figure 8.8 Same Space Consecutive Access Idle Cycle Insertion Example |
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