SH7052 datasheet(162/919 Pages) RENESAS

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8.5

Bus Arbitration

The SH7052F/SH7053F/SH7054F has a bus arbitration function that, when a bus release request

is received from an external device, releases the bus to that device. The

SH7052F/SH7053F/SH7054F also has three internal bus masters, the CPU, DMAC, and AUD.

The priority ranking for determining bus right transfer between these bus masters is:

Bus right request from external device > AUD > DMAC > CPU

Therefore, an external device that generates a bus request is given priority even if the request is

made during a DMAC burst transfer.

The AUD does not acquire the bus during DMAC burst transfer, but at the end of the transfer.

When the CPU has possession of the bus, the AUD has higher priority than the DMAC for bus

acquisition.

A bus request by an external device should be input at the

BREQ pin. The signal indicating that

the bus has been released is output from the

BACK pin.

Figure 8.9 shows the bus right release procedure.

BREQ = Low

SH7052F, SH7053F, SH7054F

BREQ accepted

Strobe pin:

high-level output

Address, data,

strobe pin:

high impedance

Bus right release

response

Bus right release status

External device

Bus right request

BACK confirmation

Bus right acquisition

BACK = Low

Figure 8.9 Bus Right Release Procedure

SH7052 Datasheet(PDF) 162 Page - Renesas Technology Corp