TLE2144MDWREP datasheet(12/22 Pages) TI

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Analog Integrated Circuit Device Data

Freescale Semiconductor

34830

FUNCTIONAL DEVICE OPERATION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

FUNCTIONAL DEVICE OPERATION

INTRODUCTION

The 34830 is a very high performance video buffer

designed for high-definition (HD) video applications. The

device features an innovative adjustable bandwidth circuitry

that allows the user to set the bandwidth of the device

through an external resistor connected to RFREQ. This

feature allows the 34830 to fit in a variety of video

applications giving it the flexibility to reduce power

consumption when full bandwidth is not required. In this way

the 34830 can support all video bandwidths, from standard

definition (SD) to high definition (HD), including the 1080i as

well as 1080p formats.

The 34830 also features an internal input clamp that works

with all sync formats and types of video signals. The clamp

can work in three different modes and allows both AC- and

DC-coupled input signals.

The 34830 is optimized to drive a single standard video

load while maintaining exceptional performance

characteristics. Two video loads can also be supported by the

device with a minimum tradeoff in performance

specifications. The 34830 supports both AC- and DC-

coupled outputs.

The 34830 can be disabled with an ultra-low current

consumption of 0.12μA, by driving the EN input to ground.

The 34830 operates using a single supply from 3V to 5.5V,

and is designed to work in the extended temperature range

from -40°C to 85°C. The device is offered in a small UDFN

package ideal to fit into space-critical applications.

The signal path of the 34830 begins with the input clamp

that DC-restores the input. The signal is then shifted up by a

level shifter which brings it to the appropriate levels required

for the output buffer. The level shifter also provides isolation

between the very sensitive input clamp circuit and the input

stage of the output buffer. The signal is then channeled to the

output buffer which amplifies it with a gain of two and drives

the output loads. Both the level shifter and output buffer

blocks are biased through the bandwidth adjust circuitry

which allows the user to set the bandwidth and quiescent

power consumption according to the application at hand.

INPUT CLAMP

The function of the input clamp is to set the DC level of the

signal at the input. The clamp can be operated in three

modes.

Sync Tip Clamp

The clamp works in this mode for Y,CV, R, G, and B

signals that are AC-coupled to the 34830. In this mode, the

clamp senses the most negative level of the input signal and

clamps it to ground. The clamp circuit does this by injecting

current into the AC-coupling capacitor to make the voltage at

the input rise. The current is disabled once the voltage has

risen to the appropriate level. The clamp circuitry includes a

small (2.0μA) pull-down current to guarantee operation of the

clamp.

Key Clamp

The clamp works in this mode for C, Pb, Pr, U, and V

signals that are AC-coupled to the 34830 while DC bias is set

externally. In this configuration, ensure that the DC bias at the

input is such that the most negative level of the signal never

goes below 50mV, to avoid interference with the clamp. The

DC bias at the input can be set through a resistive voltage

divider after the AC-coupling capacitor (Figure 23). In order to

maximize the input signal swing, it is recommended to set the

input DC bias to 0.5V. This will also maximize the swing at the

output of the 34830.

Transparent Clamp

The clamp works in this mode for all DC-biased signals.

Ensure that the most negative level of the signal is above

50mV from ground. If this requirement is not met, the signal

source and clamp both try to set the level at the input,

resulting in signal distortion. The input clamp becomes

transparent for signals above 50mV and the signal passes

through unaffected.

BIAS CIRCUITRY

The bias circuit sets the operating bias for 34830’s internal

blocks. It includes a bandgap voltage reference, a PTAT

current generator, as well as a constant current generator.

These reference currents and voltages are then distributed to

34830’s internal blocks to set their respective operating

points.

BANDWIDTH ADJUST

The 34830 features a bandwidth adjust circuit that sets the

bandwidth of the channel by adjusting quiescent supply

current. It consists of a PTAT current generator whose

current varies with the value of an external resistor (RFREQ).

This PTAT current is used to set the operating bias for the

level shifter and output buffer blocks. Increasing the external

resistor (RFREQ) lowers the bias current, and hence reduces

both supply current and bandwidth. Decreasing the value of

RFREQ increases both supply current and bandwidth. Select

a value for RFREQ in the range between 9kΩ and 108kΩ, to

set the bandwidth between the upper and lower limits. Refer

to Figure 5.

LEVEL-SHIFTER

After passing through the input clamp, which restores its

DC level to a known value, the signal is level-shifted up by

250mV. The level-shifting operation is done for two reasons.

The first is to isolate the input of the output buffer from the

sensitive clamp circuitry to prevent distortion. In this sense,

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