TS68230 datasheet(22/61 Pages) STMICROELECTRONICS

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PACR

7 6

Port A Submode

0 1

Submode 01

PACR

5 4 3

H2 Control

0 X X

Input pin - edge-sensitive status inputs, H2S is set on an asserted edge.

1 0 0

Output pin - negated, H2S is always clear.

1 0 1

Output pin - asserted, H2S is always clear.

1 1 0

Output pin - interlocked input handshake protocol, H2S is always clear.

1 1 1

Output pin - pulsed input handshake protocol, H2S is always clear.

PACR

H2 Interrupt Enable

The H2 interrupt is disabled.

The H2 interrupt is enabled.

PACR

H1 SVCRQ Enable

The H1 interrupt and DMA request are disabled.

The H1 interrupt and DMA request are enabled.

PACR

H1 Status Control

The H1S status bit is set when either the port A initial or final output latch can accept new data

It is clear when both latches are full and cannot accept new data.

The H1S status bit is one when both of the port A output latches are empty. It is clear when at

least one latch is full.

PBCR

7 6

Port B Submode

0 1

Submode 01

PBCR

5 4 3

H4 Control

0 X X

Input pin - edge-sensitive status input, H4S is set on an asserted edge.

1 0 0

Output pin - negated, H4S is always cleared.

1 0 1

Output pin - asserted, H4S is always cleared.

1 1 0

Output pin - interlocked input handshake protocol, H4S is always cleared.

1 1 1

Output pin - pulsed input handshake protocol, H4S is always cleared.

Programmable Options Mode 0 - Port A Submode 01 and Port B Submode 01

TS68230

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