TS68230 datasheet(42/61 Pages) STMICROELECTRONICS

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following the rising transition of the TIN pin after being synchronized with the internal clock. The

24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the

prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the

run or halt state.

1 1

The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is de-

cremented, rolls over, or is loaded from the counter preload registers following the rising edge of

the TIN pin after being synchronized with the internal clock. The timer enable bit determines whe-

ther the timer is in the run or halt state.

TCR

Timer Enable

Disabled

Enabled

4.10. TIMER INTERRUPT VECTOR REGISTER

(TIVR)

The timer interrupt vector register contains the 8-bit

vector supplied when the timer interrupt acknow-

ledge pin TIACK is asserted. The register is reada-

ble and writable at all times, and the same value is

always obtained from a normal read cycle or a timer

interrupt acknowledge bus cycle (TIACK). When the

RES

pin is asserted the value of $0F is loaded into the re-

gister. Refer to 5.1.3. Timer Interrupt Acknow-

ledge Cycles for more details.

4.11. COUNTER PRELOAD REGISTER H, M, L

(CPRH-L)

The counter preload registers are a group of three

8-bit registers used for storing data to be transferred

to the counter. Each of the registers is individually

addressable, or the group may be accessed with the

MOVEP.L or the MOVEP.W instructions. The ad-

dress $12 (one less than the address of CPRH) is

the null register and is reserved so that zeros are

read in the upper eight bits of the destination data

this address is ignored.

These registers are readable and writable at all

times. A read cycle proceeds independently of any

transf

r to the counter, which may be occurring simulta-

neously. To insure proper operation of the PI/T ti-

mer, a value of $000000 may not be stored in the

counter preload registers for use with the counter.

The RESET pin does not affect the contents of these

registers.

4.12. COUNT REGISTER H, M, L (CNTRH-L)

The count registers are a group of three 8-bit ad-

dresses at which the counter can be read. The

contents of the counter are not latched during a read

bus cycle ; thus, the data read at these addresses

is not guaranteed if the timer is in the run state. Write

perations to these addresses result in a normal bus

cycle but the data is ignored.

Each of the registers is individually addressable, or the

group may be accessed with the MOVEP.L or the MO-

VEP.W instructions. The address, one less than the

address CNTRH, is the null register and is reserved

so that zeros are read in the upper eight bits of the des-

tination data register when a MOVEP.L is used. Data

written to this address is ignored.

4.13. TIMER STATUS REGISTER (TSR)

The timer status register contains one bit from which

the zero detect status can be determined. The ZDS

status bit (bit 0) is an edge-sensitive flip-flop that is

set to one when the 24-bit counter decrements from

$000001 to $000000. The ZDS status bit is cleared

to zero following the direct reset operation or when

the timer is halted. Note that when the RESET pin

is asserted the timer is disabled, and thus enters the

halt state.

This register is always readable without conse-

quence. A write access performs a direct reset ope-

ration if bit 0 in the written data is one. Following that,

65432

Bit

Bit 9

Bit

Bit 8

CPRH

CPRM

CPRL

4321

Bit

Bit 9

Bit

Bit 8

ZDS

CNTRH

CPRM

CPRL

TS68230

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