TS68230 datasheet(52/61 Pages) STMICROELECTRONICS

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6.6. AC ELECTRICAL SPECIFICATIONS

(VCC = 5.0Vdc ± 5%, VSS = 0Vdc, TA =TL to TH unless otherwise noted)

Peripheral Input Timings (figures 6.4)

8MHz

10MHz

Number

Parameter

Min.

Max.

Min.

Max.

Unit

Port Input Data Valid to H1(H3) Asserted (setup time)

100

H1(H3) Asserted to Port Input Data Invalid (hold time)

Handshake Input H1(H4) Pulse Width Asserted

Handshake Input H1(H4) Pulse Width Negated

H1(H3) Asserted to H2(H4) Negated (delay time)

150

120

CLK Low to H2(H4) Asserted (delay time)

100

(1 )

H2(H4) Asserted to H1(H3) Asserted

(2 )

CLK Low to H2(H4) Pulse Negated (delay time)

125

(3 . 4 )

Synchronized H1(H3) to CLK low on which DMAREQ is asserted

2.5

3.5

2.5

3.5

CLK Per

CLK low on which DMAREQ is asserted to CLK low on which

DMAREQ is negated

2.5

CLK Per

(5 )

H1(H3) Asserted to CLK High (setup time)

(3 . 4 )

Synchronized H1(H3) to CLK low on which H2(H4) is asserted

3.5

4.5

3.5

4.5

CLK Per

CLK Low to DMAREQ Low (delay time)

120

100

CLK Low to DMAREQ High (delay time)

120

100

If these two signals are derived from different sources they will have different instantaneous frequency variations. In

this case the frequency applied to the TIN pin must be distinctly less than the frequency at the CLK pin to avoid lost

cycles of the TIN signal. With signals derived from different crystal oscillators applied to the TIN and CLK pins with

fast rise and fall times, the TIN frequency can approach 80 to 90% of the frequency of the CLK signal without a loss

of a cycle of the TIN signal.

If these signals are derived from the same frequency source then the frequency of the signal applied to TIN can be

100% of the frequency at the CLK pin. They may be generated by different buffers from the same signal or one

may be an inverted version of the other. The TIN signal may be generated by an ’AND’ function of the clock and a

control signal.

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