MPC8640DEC datasheet(47/140 Pages) FREESCALE

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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

Local Bus

Table 41. Local Bus Timing Parameters—PLL Bypassed

Parameter

Symbol 1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Local bus duty cycle

tLBKH/tLBK

Internal launch/capture clock to LCLK delay

tLBKHKT

2.3

3.9

Input setup to local bus clock (except

LGTA/LUPWAIT)

tLBIVKH1

5.7

—

4, 5

LGTA/LUPWAIT input setup to local bus

clock

tLBIVKL2

5.6

—

4, 5

Input hold from local bus clock (except

LGTA/LUPWAIT)

tLBIXKH1

-1.8

—

4, 5

LGTA/LUPWAIT input hold from local bus

clock

tLBIXKL2

-1.3

—

4, 5

LALE output transition to LAD/LDP output

transition (LATCH hold time)

tLBOTOT

1.5

—

Local bus clock to output valid (except

LAD/LDP and LALE)

tLBKLOV1

—-0.3

Local bus clock to data valid for LAD/LDP

tLBKLOV2

—-0.1

Local bus clock to address valid for LAD

tLBKLOV3

—0

Local bus clock to LALE assertion

tLBKLOV4

—0

Output hold from local bus clock (except

LAD/LDP and LALE)

tLBKLOX1

-3.2

—

Output hold from local bus clock for

LAD/LDP

tLBKLOX2

-3.2

—

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

tLBKLOZ1

—0.2

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