AT89C5131A-RDTUM datasheet(80/188 Pages) ATMEL

80 / 188 page

4337K–USB–04/08

AT89C5130A/31A-M

Each interrupt source can also be individually programmed to one out of four priority levels by

setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority

High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with

each combination.

16.2

Registers

The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at

address 004BH and Keyboard interrupt vector is located at address 003BH. All other vectors

addresses are the same as standard C52 devices.

Table 16-1.

Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-

ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of

higher priority level is serviced. If interrupt requests of the same priority level are received simul-

taneously, an internal polling sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the polling sequence.

Table 16-2.

IEN0 Register

IEN0 - Interrupt Enable Register (A8h)

IPH.x

IPL.x

Interrupt Level Priority

0 (Lowest)

3 (Highest)

ET2

ET1

EX1

ET0

EX0

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