AT89C5131A-RDTUM datasheet(15/188 Pages) ATMEL

15 / 188 page

4337K–USB–04/08

AT89C5130A/31A-M

In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out-

put is not selected for the USB device.

Figure 5-2.

Crystal Connection

5.3

PLL

5.3.1

PLL Description

The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock)

synchronized with an external low-frequency (the Peripheral Clock). The PLL clock is used to

generate the USB interface clock. Figure 5-3 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the

comparison between the reference clock coming from the N divider and the reverse clock com-

ing from the R divider and generates some pulses on the Up or Down signal depending on the

edge position of the reverse clock. The PLLEN bit in PLLCON register is used to enable the

clock generation. When the PLL is locked, the bit PLOCK in PLLCON register (see Figure 5-3) is

set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by inject-

ing or extracting charges from the external filter connected on PLLF pin (see Figure 5-4). Value

of the filter components are detailed in the Section “DC Characteristics”.

The VCO block is the Voltage Controlled Oscillator controlled by the voltage VREF produced by

the charge pump. It generates a square wave signal: the PLL clock.

Figure 5-3.

PLL Block Diagram and Symbol

VSS

PLLEN

PLLCON.1

N3:0

N divider

R divider

VCO

USB Clock

USBclk

OSC

clk

(

)

-----------------------------------------------

OSC

CLOCK

PFLD

PLOCK

PLLCON.0

PLLF

CHP

Vref

Down

R3:0

USB

CLOCK

USB Clock Symbol

AT89C5131A-RDTUM Datasheet(PDF) 15 Page - ATMEL Corporation

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