AT89C5131A-RDTUM datasheet(104/188 Pages) ATMEL

104 / 188 page

104

4337K–USB–04/08

AT89C5130A/31A-M

20.1

Description

The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the

Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data regis-

ter (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 20-

12) and the Synchronous Serial Address register (SSADR Table 20-13).

SSCON is used to enable the TWI interface, to program the bit rate (see Table 20-3), to enable

slave modes, to acknowledge or not a received data, to send a START or a STOP condition on

the 2-wire bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI

module.

SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire bus.

The three least significant bits are always zero. The five most significant bits contains the status

code. There are 26 possible status codes. When SSCS contains F8h, no relevant state informa-

tion is available and no serial interrupt is requested. A valid status code is available in SSCS one

machine cycle after SI is set by hardware and is still present one machine cycle after SI has

been reset by software. to Table 20-9. give the status for the master modes and miscellaneous

states.

SSDAT contains a byte of serial data to be transmitted or a byte which has just been received. It

is addressable while it is not in process of shifting a byte. This occurs when 2-wire logic is in a

defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SI is

set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always

contains the last byte present on the bus.

SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the TWI

module will respond when programmed as a slave transmitter or receiver. The LSB is used to

enable general call address (00h) recognition.

Figure 20-3 shows how a data transfer is accomplished on the 2-wire bus.

Figure 20-3. Complete Data Transfer on 2-wire Bus

The four operating modes are:

• Master Transmitter

• Master Receiver

• Slave transmitter

• Slave receiver

Data transfer in each mode of operation is shown in Table to Table 20-9 and Figure 20-4. to

Figure 20-7.. These figures contain the following abbreviations:

: START condition

SDA

SCL

start

condition

MSB

ACK

acknowledgement

signal from receiver

acknowledgement

signal from receiver

3-8

ACK

stop

condition

clock line held low

while interrupts are serviced

AT89C5131A-RDTUM Datasheet(PDF) 104 Page - ATMEL Corporation

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