AT89C5131A-RDTUM datasheet(120/188 Pages) ATMEL

120 / 188 page

120

4337K–USB–04/08

AT89C5130A/31A-M

21. USB Controller

21.1

Description

The USB device controller provides the hardware that the AT89C5131 needs to interface a USB

link to a data flow stored in a double port memory (DPRAM).

The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the

AT89C5131 PLL (see Section “PLL”, page 15) divided by a clock prescaler. This clock is used to

generate a 12 MHz Full-speed bit clock from the received USB differential data and to transmit

data according to full speed USB device tolerance. Clock recovery is done by a Digital Phase

Locked Loop (DPLL) block, which is compliant with the jitter specification of the USB bus.

The Serial Interface Engine (SIE) block performs NRZI encoding and decoding, bit stuffing, CRC

generation and checking, and the serial-parallel data conversion.

The Universal Function Interface (UFI) realizes the interface between the data flow and the Dual

Port RAM.

Figure 21-1. USB Device Controller Block Diagram

21.1.1

Serial Interface Engine (SIE)

The SIE performs the following functions:

• NRZI data encoding and decoding.

• Bit stuffing and un-stuffing.

• CRC generation and checking.

• Handshakes.

• TOKEN type identifying.

SIE

DPLL

USB

D+/D-

Buffer

UFI

12 MHz

48 MHz +/- 0.25%

D+

Up to 48 MHz

UC_sysclk

C51

Microcontroller

Interface

D-

AT89C5131A-RDTUM Datasheet(PDF) 120 Page - ATMEL Corporation