AT89C5131A-RDTUM datasheet(140/188 Pages) ATMEL

140 / 188 page

140

4337K–USB–04/08

AT89C5130A/31A-M

Table 21-4.

USBINT Register

USBINT (S:BDh)

USB Global Interrupt Register

Reset Value = 00h

WUPCPU

EORINT

SOFINT

SPINT

Bit Number

Bit

Mnemonic

Description

7-6

Reserved

The value read from these bits is always 0. Do not set these bits.

WUPCPU

Wake Up CPU Interrupt

This bit is set by hardware when the USB controller is in SUSPEND state and is re-

activated by a non-idle signal FROM USB line (not by an upstream resume). This

triggers a USB interrupt when EWUPCPU is set in Figure 21-5 on page 141.

When receiving this interrupt, user has to enable all USB clock inputs.

This bit will be cleared by software (USB clocks must be enabled before).

EORINT

End Of Reset Interrupt

This bit is set by hardware when a End Of Reset has been detected by the USB

controller. This triggers a USB interrupt when EEORINT is set (see Table 21-5 on page

141).

This bit will be cleared by software.

SOFINT

Start of Frame Interrupt

This bit is set by hardware when an USB Start of Frame PID (SOF) has been detected.

This triggers a USB interrupt when ESOFINT is set (see Table 21-5 on page 141).

This bit will be cleared by software.

Reserved

The value read from this bit is always 0. Do not set this bit.

Reserved

The value read from this bit is always 0. Do not set this bit.

SPINT

Suspend Interrupt

This bit is set by hardware when a USB Suspend (Idle bus for three frame periods: a J

state for 3 ms) is detected. This triggers a USB interrupt when ESPINT is set in see

Table 21-5 on page 141.

This bit will be cleared by software BEFORE any other USB operation to re-activate the

macro.

AT89C5131A-RDTUM Datasheet(PDF) 140 Page - ATMEL Corporation

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