6

© 2008 Semtech Corp.

www.semtech.com

SC4612H

POWER MANAGEMENT

Pin Descriptions

Pin #

MLPD

Pin#

SOIC

Pin Name

Pin Function

1, 7

NC

No connection.

1

2

ILIM

The current limit programing resistor at this pin in conjunction with an internal current

source programs the current limit threshold for the low side MOSFET R

DS-ON

sensing.

Once the voltage drop across the bottom MOSFET is larger than the programmed value,

current limit condition occurs, and the hiccup current limit protection is activated.

2

3

OSC

Oscillator Frequency set pin. An external capacitor to GND will program the oscillator

frequency. See Table 1 "Frequency vs. C

3

4

SS/EN

Soft Start pin. Internal current source connected to a single external capacitor will

determine the soft-start duration for the output. Inhibits the chip if pulled down.

4

5

EAO

Error Amplifier Output. A compensation network is connected from this pin to FB.

5

8

FB

The inverting input of the error amplifier. Feedback pin is used to sense the output

voltage via a resistive divider.

6

6

VDD

Bias supply. Also, VDD pin is internally used to provide the base drive to the internal

pass transistor regulating the DRV supply.

7

9

GND

Ground.

8

10

DL

Drive Low. Gate drive for bottom MOSFET.

9

11

DRV

DRV supplies the external MOSFETs gate drive and the chips internal circuitry. This pin

should be bypassed with a ceramic capacitor to GND. DRV is internally regulated from

the external supply connected to VDD. If VDD is below 10V, the supply should be directly

connected to the DRV pin.

10

12

BST

BST signal. Supply for high side driver; can be directly connected to an external supply

or to a bootstrap circuit.

11

13

DH

Drive High. Gate drive for top MOSFET.

12

14

PHASE

The return path for the high side gate drive, also used to sense the voltage at the phase

node for adaptive gate drive protection and the low-side R

X

N/A

THERMAL

PAD (GND)

Pad for heatsinking purposes. Connect to ground plane using multiple vias.

SS

SS

SS

I

2

.

1

X

C

T

≈