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6090D–DRMSD–12-Feb-07

ATSAM3308B

10.4

Serial Slave Synchronous Interface

The ATSAM3308B can be controlled by an external host processor through this unidirectional

serial interface. However, no firmware can be downloaded at power-up through this interface.

Therefore an external ROM/Flash/EEPROM is required.

Pins used: SCLK, SYNC, SDIN (input) INT (output)

Data is shifted into MSB first. The IC samples an incoming SDIN bit on the rising edge of SCLK,

therefore the host should change SDIN on the negative SCLK edge.

SYNC allows initial synchronization. The rising edge of SYNC, which should occur with SCLK

low, indicates that SDIN will hold MSB data on the next rising SCLK.

The data is stored internally into a 256 byte FIFO.

When the FIFO count is below 64, the INT output goes low. This allows the host processor to

send data in burst mode.

The maximum SCLK frequency is fck (fck being the crystal frequency).The minimum time

between two bytes is 64 fck periods.

The contents of the SDIN data are defined by the firmware.

Figure 10-4.

Serial Slave Interface Typical Timing

10.5

Digital Audio

Pins used: CLBD (output), WSBD (output) DABD3 - 0 (outputs) DAAD3 - 0 (inputs)

Optionally: CLAD3 - 0 (inputs), WSAD3 - 0 (inputs)

The ATSAM3308B allows for 8 digital audio output channels and 8 digital audio input channels.

All audio channels are normally synchronized on single clocks CLBD, WSBD which are derived

from the IC crystal oscillator. However, as a firmware option, the DAAD3 - 0 inputs can be syn-

chronized with incoming CLAD3 - 0 and WSAD3 - 0 signals. In this case, the incoming sampling

frequencies must be lower or equal to the chip sampling frequency.

The digital audio timing follows the I2S standard, with up to 24 bits per sample

SCLK

SYNC

SDIN

MSB