AT91SAM9261 datasheet(20/43 Pages) ATMEL

20 / 43 page

6062KS–ATARM–15-Jan-09

AT91SAM9261 Preliminary

8.1.2

Boot Strategies

The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,

the memory layout can be configured with two parameters.

REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This

is done by software once the system has booted for each Master of the Bus Matrix. Refer to the

Bus Matrix Section for more details.

When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an

external memory. This is done via hardware at reset.

Note:

Memory blocks not affected by these parameters can always be seen at their specified base

addresses. See the complete memory map presented in Figure 8-1 on page 16.

The AT91SAM9261 Bus Matrix manages a boot memory that depends on the level on the BMS

pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is

reserved for this purpose.

If BMS is detected at 1, the boot memory is the embedded ROM.

If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the

External Bus Interface.

8.1.2.1

BMS = 1, Boot on Embedded ROM

The system boots using the Boot Program.

• DataFlash Boot

– Downloads and runs an application from SPI DataFlash into internal SRAM

– Downloaded code size from SPI DataFlash depends on embedded SRAM

–size

– Automatic detection of valid application

– SPI DataFlash connected to SPI NPCS0

• NANDFlash Boot

• Boot Uploader in case no valid program is detected in external SPI DataFlash

– Small monitor functionalities (read/write/run) interface with SAM-BA

™ application

– Automatic detection of the communication link

Serial communication on a DBGU (XModem protocol)

USB Device Port (CDC Protocol)

8.1.2.2

BMS = 0, Boot on External Memory

• Boot on slow clock (32,768 Hz)

• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit

data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.

The customer-programmed software must perform a complete configuration.

To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take

the following steps:

Program the PMC (main oscillator enable or bypass mode).

Program and start the PLL.

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