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LT3751

3751f

APPLICATIONS INFORMATION

Output Diode Selection

The output diode(s) are selected based on the maximum

repetitive reverse voltage (VRRM) and the average forward

current (IF(AV)). The output diode’s VRRM should exceed

VOUT + N • VTRANS. The output diode’s IF(AV) should exceed

IPK/2N,theaverageshort-circuitcurrent.Theaveragediode

current is also a function of the output voltage.

IAVG =

IPK •VTRANS

2•(VOUT +N• VTRANS)

The highest average diode current occurs at low output

voltages and decreases as the output voltage increases.

Reverse recovery time, reverse bias leakage and junc-

tion capacitance should also be considered. All affect

the overall charging efﬁciency. Excessive diode reverse

recovery times can cause appreciable discharging of the

output capacitor, thereby increasing charge time. Choose

a diode with a reverse recovery time of less than 100ns.

Diode leakage current under high reverse bias bleeds the

output capacitor of charge and increases charge time.

Choose a diode that has minimal reverse bias leakage

current. Diode junction capacitance is reﬂected back to

the primary, and energy is lost during the NMOS intrinsic

diode conduction. Choose a diode with minimal junction

capacitance. Table 3 recommends several output diodes

for various output voltages that have adequate reverse

recovery times.

Table 3. Recommended Output Diodes

MANUFACTURER

PART NUMBER

IF(AV) (A)

VRRM (V)

TRR (ns)

PACKAGE

Central Semiconductor

www.centralsemi.com

CMR1U-10M

1000

100

SMA

Fairchild Semiconductor

www.fairchildsemi.com

ES3J

ES1G

ES1J

600

400

600

SMC

SMA

On Semiconductor

www.onsemi.com

MURS360

MURA260

MURA160

600

SMC

SMA

Vishay

www.vishay.com

USB260

US1G

US1M

GURB5H60

600

400

1000

600

SMB

SMA

TO-263AB

Setting Current Limit

Placing a sense resistor from the positive sense pin, CSP,

to the negative sense pin, CSN, sets the maximum peak

switch current. The maximum current limit is nominally

106mV/RSENSE. The power rating of the current sense

resistor must exceed:

PRSENSE ≥

I2PK •RSENSE

VOUT(PK)

VOUT(PK) +N• VTRANS

⎛

⎝

⎜

⎞

⎠

⎟

Additionally, there is approximately a 100ns propagation

delay from the time that peak current limit is detected to

when the gate transitions to the low state. This delay in-

creases the peak current limit by (VTRANS)(100ns)/LPRI.

Sense resistor inductance (LRSENSE) is another source of

current limit error. LRSENSE creates an input offset voltage

(VOS) to the current comparator and causes the current

comparator to trip early. VOS can be calculated as:

VOS = VTRANS •

LRSENSE

LPRIMARY

⎛

⎝⎜

⎞

⎠⎟

The change in current limit becomes VOS/RSENSE.Theerror

is more signiﬁcant for applications using large di/dt ratios

in the transformer primary. It is recommended to use very

low inductance (< 2nH) sense resistors. Several resistors

can be placed in parallel to help reduce the inductance.

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